Stack memory design for a low-cost instruction folding Java processor

Zi Gang Lin*, Han Wen Kuo, Zi Jing Guo, Chun-Jen Tsai

*此作品的通信作者

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose the design of the stack memory for a low-cost Java processor that explores instruction-level parallelism. The Java virtual machine (JVM) is a stack machine where the instruction execution pipeline uses a stack to store intermediate computation results and local variables. High performance Java processors often use a large stack cache to enable parallel accesses to operands and local variables to achieve instruction-level parallelism. We propose a low-cost alternative of stack memory design that allows the Java processor to access the critical stack operands and local variables concurrently. The stack memory is constructed using seven registers and two blocks of dual-port on-chip SRAM; and is optimized for the Java instruction set architecture. When coupled with a low-cost two-way instruction folding pipeline, micro-benchmark results show that the proposed architecture can achieve up to 45.4% 2-fold instruction folding rate.

原文English
頁面3226-3229
頁數4
DOIs
出版狀態Published - 28 九月 2012
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 20 五月 201223 五月 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家/地區Korea, Republic of
城市Seoul
期間20/05/1223/05/12

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