In this paper, we propose the design of the stack memory for a low-cost Java processor that explores instruction-level parallelism. The Java virtual machine (JVM) is a stack machine where the instruction execution pipeline uses a stack to store intermediate computation results and local variables. High performance Java processors often use a large stack cache to enable parallel accesses to operands and local variables to achieve instruction-level parallelism. We propose a low-cost alternative of stack memory design that allows the Java processor to access the critical stack operands and local variables concurrently. The stack memory is constructed using seven registers and two blocks of dual-port on-chip SRAM; and is optimized for the Java instruction set architecture. When coupled with a low-cost two-way instruction folding pipeline, micro-benchmark results show that the proposed architecture can achieve up to 45.4% 2-fold instruction folding rate.
|出版狀態||Published - 28 九月 2012|
|事件||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
持續時間: 20 五月 2012 → 23 五月 2012
|Conference||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|國家/地區||Korea, Republic of|
|期間||20/05/12 → 23/05/12|