@inproceedings{01d2eb9951264cac8974fffee38821ef,
title = "Source-side engineering to increase holding voltage of LDMOS in a O.5-m 16-V BCD technology to avoid latch-up failure",
abstract = "To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a O.5-μm 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5V to 16.2V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit",
author = "Chen, {Wen Yi} and Ming-Dou Ker and Jou, {Yeh Ning} and Huang, {Yeh Jen} and Lin, {Geeng Lih}",
year = "2009",
month = nov,
day = "16",
doi = "10.1109/IPFA.2009.5232701",
language = "English",
isbn = "9781424439102",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
pages = "41--44",
booktitle = "Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009",
note = "2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009 ; Conference date: 06-07-2009 Through 10-07-2009",
}