SoC memory system design

As the increasing integration density of various IPs into the SoC, the memory system becomes a dominant role to determine the final performance, area, and power consumption of SoC. The memory system design involves various aspects, from bottom level on-chip or off-chip memory technologies, to the high level memory optimization and management. Between the two levels is the memory controller to efficiently deliver the required data within the power and delay constraints. The PC-driven off-chip memory continues its high density and high bandwidth development track. However, it also adapts its interface and power to be either fast random access or low power consumption to fit into the divergent needs of various SoC applications. The embedded memory now is driven by the SoC and thus becomes more integration friendly, either at the interface or at the process technologies. Memory optimization and management optimizes the memory access by high level reordering, remapping and memory size compression. Power of the memory system can be further reduced by transition reduction of memory bus and dynamic power management of memory systems. Further optimization of memory access needs the memory controller to fully utilize the available bandwidth. Since the components in SoC have divergent needs, either bandwidth sensitive, or latency sensitive, the memory controller design also quick evolves to be a more intelligent one to provide the different quality and latency guaranteed access. The optimization of memory system is part of the complex SoC design problem, which can only be analyzed and solved within the target applications