TY - GEN
T1 - SMALL GEOMETRY MOS TRANSISTOR MEASUREMENTS AND OBSERVED SHORT AND NARROW CHANNEL EFFECTS.
AU - Iwai, H.
AU - Oristian, J.
AU - Walker, J.
AU - Dutton, R.
PY - 1984
Y1 - 1984
N2 - Summary form only given. The effect of short and narrow channels on MOS transistor capacitance are discussed. To identify the short-channel effect, transistors with 100 mu m width and L//e //f //f of 7. 8 mu m, 3. 8 mu m, 1. 8 mu m, and 0. 8 mu m, were measured. Just above the threshold voltage, C//g //d decreases. This may be due to the shielding effect of the channel connected to source. The most significant short-channel effect is that the distinction between the saturation and linear region becomes vague. This agrees with the dc characteristics. As a result, C//g //d begins to increase in the saturation region. Narrow-channel devices with L = 100 mu m and several W//e //f //f from 9. 2 mu m to 1. 2 mu m were measured and normalized. Normalized C//g //s for the narrow device is larger because of the fringing portion along the field edge. In addition, the narrow C//g //s increases with V//g significantly. Presumably this is due to the inversion layer width increasing with gate voltage.
AB - Summary form only given. The effect of short and narrow channels on MOS transistor capacitance are discussed. To identify the short-channel effect, transistors with 100 mu m width and L//e //f //f of 7. 8 mu m, 3. 8 mu m, 1. 8 mu m, and 0. 8 mu m, were measured. Just above the threshold voltage, C//g //d decreases. This may be due to the shielding effect of the channel connected to source. The most significant short-channel effect is that the distinction between the saturation and linear region becomes vague. This agrees with the dc characteristics. As a result, C//g //d begins to increase in the saturation region. Narrow-channel devices with L = 100 mu m and several W//e //f //f from 9. 2 mu m to 1. 2 mu m were measured and normalized. Normalized C//g //s for the narrow device is larger because of the fringing portion along the field edge. In addition, the narrow C//g //s increases with V//g significantly. Presumably this is due to the inversion layer width increasing with gate voltage.
UR - http://www.scopus.com/inward/record.url?scp=0021640118&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0021640118
SN - 4930813085
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 78
EP - 79
BT - Digest of Technical Papers - Symposium on VLSI Technology
PB - Business Cent for Academic Soc Japan
ER -