Skillfully diminishing antenna effect in layer assignment stage

Chih Chien Lin, Wen Hao Liu, Yih-Lang Li

研究成果: Conference contribution同行評審

摘要

Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.

原文English
主出版物標題Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
發行者IEEE Computer Society
ISBN(列印)9781479927760
DOIs
出版狀態Published - 2014
事件2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
持續時間: 28 4月 201430 4月 2014

出版系列

名字Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
國家/地區Taiwan
城市Hsinchu
期間28/04/1430/04/14

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