Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits.