Single-ended subthreshold SRAM with asymmetrical write/read-assist

Ming Hsien Tu; Jihi Yu Lin; Ming Chien Tsai; Shyh-Jye Jou; Ching Te Chuang

doi:10.1109/TCSI.2010.2071690

Single-ended subthreshold SRAM with asymmetrical write/read-assist

Ming Hsien Tu^*, Jihi Yu Lin, Ming Chien Tsai, Shyh-Jye Jou, Ching Te Chuang

^*此作品的通信作者

研究成果: Article › 同行評審

123 引文斯高帕斯（Scopus）

摘要

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V_DD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

原文	English
文章編號	5634142
頁（從 - 到）	3039-3047
頁數	9
期刊	IEEE Transactions on Circuits and Systems I: Regular Papers
卷	57
發行號	12
DOIs	https://doi.org/10.1109/TCSI.2010.2071690
出版狀態	Published - 2010

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abstract = "In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.",

keywords = "Low power, low voltage, single-ended SRAM",

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AU - Tu, Ming Hsien

AU - Lin, Jihi Yu

AU - Tsai, Ming Chien

AU - Jou, Shyh-Jye

AU - Chuang, Ching Te

PY - 2010

Y1 - 2010

N2 - In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

AB - In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

KW - Low power

KW - low voltage

KW - single-ended SRAM

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JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 12

M1 - 5634142

ER -

Single-ended subthreshold SRAM with asymmetrical write/read-assist

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