An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.
|頁（從 - 到）||545-548|
|期刊||Proceedings of the Custom Integrated Circuits Conference|
|出版狀態||Published - 1 1月 1998|
|事件||Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
持續時間: 11 5月 1998 → 14 5月 1998