Simultaneous Switching Noise analysis and low bouncing buffer design

Shyh-Jye Jou; Wei Chung Cheng; Yu Tao Lin

doi:10.1109/CICC.1998.695037

Simultaneous Switching Noise analysis and low bouncing buffer design

Shyh-Jye Jou^*, Wei Chung Cheng, Yu Tao Lin

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電子研究所

研究成果: Conference article › 同行評審

12 引文斯高帕斯（Scopus）

摘要

An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

原文	English
頁（從 - 到）	545-548
頁數	4
期刊	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1998.695037
出版狀態	Published - 1 1月 1998
事件	Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA 持續時間: 11 5月 1998 → 14 5月 1998

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10.1109/CICC.1998.695037

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abstract = "An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.",

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AU - Cheng, Wei Chung

AU - Lin, Yu Tao

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N2 - An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

AB - An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

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M3 - Conference article

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T2 - Proceedings of the 1998 IEEE Custom Integrated Circuits Conference

Y2 - 11 May 1998 through 14 May 1998

ER -

Simultaneous Switching Noise analysis and low bouncing buffer design

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