Simultaneous switching noise analysis and low-bounce buffer design

An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications.