Simulation-based functional test generation for embedded processors

Charles H.P. Wen*, Li C. Wang, Kwang Ting Cheng

*此作品的通信作者

研究成果: Article同行評審

35 引文 斯高帕斯(Scopus)

摘要

Deterministic functional test pattern generation has been a long-standing open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key in developing a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the design size. This work proposes a novel functional test generation approach where simulation results are used to guide the generation of additional tests. Our methodology avoids the complexity growth issue by converting some modules in a design into simpler and more efficient models. Then, these models are used to facilitate the actual test generation process. We develop two sets of techniques to achieve these conversions: Boolean learning for random logic and arithmetic learning for datapath modules. We demonstrate the effectiveness and discuss the limitations of these techniques through experiments on benchmark circuits. Last, we validate the overall test generation methodology based on the OpenRISC 1200 microprocessor.

原文English
頁(從 - 到)1335-1343
頁數9
期刊IEEE Transactions on Computers
55
發行號11
DOIs
出版狀態Published - 1 十一月 2006

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