Simulatable timing model for MOS logic circuit

Shyh-Jye Jou, Wen Zen Shen, Chein Wei Jen, Chung Len Lee

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)


A simulatable logic circuit timing model is presented. This timing model is derived from the timing behaviour of MOS devices during transients. Analyses of the errors produced by the use of Newton-Raphson methods to linearise MOS devices and numerical integration algorithms to discretise derivative operators are carried out. Based on these analyses and simulation results the best algorithms are chosen to construct the simulatable timing model. This simulatable timing model consists only of conductances and independent current sources, so is easily incorporated with a lookup table model. A local variable time step control scheme based on the characteristics of the parameters and a simple equation, is implemented, to enhance the simulation speed. A simulator is implemented and the simulated results show that its simulation speed is over 200 times faster than SPICE2G.5 with comparable accuracy.

頁(從 - 到)276-284
期刊IEE Proceedings G: Electronics Circuits and Systems
出版狀態Published - 1987


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