@inproceedings{1c47431cf4cd4915b892f73d088028de,
title = "Silicon Nitride-induced Threshold Voltage Shift in p-GaN HEMTs with Au-free Gate-first Process",
abstract = "In this work, we observe the distinct VTH characteristics in the Au-free gate-first processing p-GaN/AIGaN/GaN HEMTs with two commonly used passivation layers, i.e., SiN and SiO2. The device with SiN shows a depletion-mode (D-mode) characteristic (VTH ∼ -5V) whereas the device with SiO2 passivation exhibits an enhancement-mode (E-mode) characteristic (VTH ∼ +0.7V). Furthermore, Transmission Line Measurement (TLM) devices are fabricated to investigate the effects of the passivation on two dimensional electron gas (2DEG) in p-GaN/AIGaN/GaN stack. The results indicate that a low Rsh is obtained while passivating device surface with SiN layer, suggesting that 2DEG is present, which is most probably due to an unfunctional p-GaN layer. The SIMS results indicate a high H-intensity in the p-GaN/AIGaN/GaN stack with a SiN passivation layer. Thus, P-GaN deactivation due to the formation of complex Mg-H after SiN passivation is proposed to explain the D-mode characteristic in the device with a SiN passivation layer. ",
keywords = "Au-free, p-GaN HEMTs, passivation, SiN, SiO2, threshold voltage shift",
author = "Chen, {Yi Cheng} and Tang, {Shun Wei} and Lin, {Pin Hau} and Chen, {Zheng Chen} and Lu, {Ming Hao} and Kao, {Kuo Hsing} and Wu, {Tian Li}",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020 ; Conference date: 20-07-2020 Through 23-07-2020",
year = "2020",
month = jul,
day = "20",
doi = "10.1109/IPFA49335.2020.9260944",
language = "English",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020",
address = "美國",
}