High-performance SerDes with both high area efficiency (mm2/lane) and energy efficiency (pJ/b) are driven by the ever-increasing demands of bandwidth and capacity in data centers. They also enable chiplets, multi-die, and silicon-photonics integration for a low cost, high yield, and high throughput solution. Besides, low-power SerDes is essential to overall system power savings by reducing the power overhead and cost for cooling. This session introduces advanced wireline techniques that support both high-speed and energy-efficient data transmission over electrical, fiber, and dielectric waveguide channels. The first three papers of the session describe short-reach power- and density-optimized transceivers in state-of-the-art 7nm FinFET technology. The next two describe low-power clock generators for high-speed transceivers. The remaining four papers of the session focus on design solutions to enable future high-speed link scaling, including optical and dielectric waveguides, ultra-low power CDRs, and the potential for >50Gb/s simultaneous, bidirectional signaling over high-loss channels.
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|Digest of Technical Papers - IEEE International Solid-State Circuits Conference
|Published - 13 2月 2021
|2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States
持續時間: 13 2月 2021 → 22 2月 2021