Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors

Chris Chun Chih Chung, Chun Ming Ko, Tien Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and Ioff is drastically reduced (two orders of magnitude) with increasing trimming cycles. Full silicidation on the source/drain (FUSI-S/D) is performed to improve Ion. Surprisingly, after silicidation, both Ion and boldsymbolmu _mathrm FE shows degradation despite that the series resistance is improved. An ultrathin body junctionless (UTB-JL) device is fabricated to investigate the degradation cause by direct CV measurement on the device, which can give us an insight into the details of the change with the silicidation.

原文English
文章編號8843925
頁(從 - 到)959-963
頁數5
期刊IEEE Journal of the Electron Devices Society
7
發行號1
DOIs
出版狀態Published - 2019

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