Self-Aligned Mesfets By A Dual-Level Double-Lift-Off Substitutional Gate (Dds) Technique For High-Speed Low-Power Gaas Ics

Mau-Chung Chang, F. J. Ryan, R. P. Vahrenkamp, C. G. Kirkpatrick

    研究成果: Article同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    A new self-aligned substitutional gate processing technique which involves dual-level resist patterning was developed for 75 mm (3 in)-diameter GaAs MESFETs IC fabrication. The transconductance of 1 μm gate length DDS E-MESFETs reached a maximum value of 280 mS/mm. E/R ring oscillators showed a 22 ps/gate propagation delay and a 34.5 fJ speed-power product. E/D ring oscillators had a 53 ps/gate propagation delay, a 12.5 fJ speed-power product and a power dissipation of 0.24 mW/gate at 300 K.

    原文English
    頁(從 - 到)354-356
    頁數3
    期刊Electronics Letters
    21
    發行號8
    DOIs
    出版狀態Published - 1 1月 1985

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