@inproceedings{4ec60757507f418ca756137d804cc702,
title = "SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism",
abstract = "In modern VLSI design flow, timing analysis is crucial for verifying whether a circuit design can operate without errors. Soft-delay effect (SDE), which is a kind of degraded soft error, will make system failed though the circuit has passed the typical timing analysis. Therefore, we propose a soft-delay-aware timing analysis which takes SDE into consideration. Additionally, a path-fixing mechanism is also proposed to fix up the violated paths automatically. Experimental results show that only 1.05% area budget is required averagely that all violated paths can be fixed up. In summary, SDPTA and the path-fixing mechanism are capable of reducing SDE to general circuits without other manual effort. ",
keywords = "gate sizing, soft delay, soft error, timing analysis",
author = "Huang, {Gary K.C.} and Lin, {Dave Y.W.} and Tang, {John Z.L.} and Wen, {Charles H.P.}",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.; 29th IEEE Asian Test Symposium, ATS 2020 ; Conference date: 22-11-2020 Through 25-11-2020",
year = "2020",
month = nov,
day = "23",
doi = "10.1109/ATS49688.2020.9301512",
language = "English",
series = "Proceedings of the Asian Test Symposium",
publisher = "IEEE Computer Society",
booktitle = "Proceedings - 2020 IEEE 29th Asian Test Symposium, ATS 2020",
address = "美國",
}