Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

Shiyang Zhu; Jingde Chen; H. Y. Yu; S. J. Whang; J. H. Chen; C. Shen; M. F. Li; S. J. Lee; Chunxiang Zhu; D. S.H. Chan; Anyan Du; C. H. Tung; Jagar Singh; Albert Chin; D. L. Kwong

doi:10.1109/ICSICT.2004.1434952

Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

Shiyang Zhu^*
, Jingde Chen
, H. Y. Yu
, S. J. Whang
, J. H. Chen
, C. Shen
, M. F. Li
, S. J. Lee
, Chunxiang Zhu
, D. S.H. Chan
, Anyan Du
, C. H. Tung
, Jagar Singh
, Albert Chin
, D. L. Kwong

^*此作品的通信作者

研究成果: Paper › 同行評審

摘要

Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO ₂ gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of I _on ∼10 ⁷-10 ⁸ and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi _2-x silicide have also demonstrated a very promising characteristic with a recorded high I _on/I _off radio of∼ 10 ⁷ and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

原文	English
頁面	53-56
頁數	4
DOIs	https://doi.org/10.1109/ICSICT.2004.1434952
出版狀態	Published - 10月 2004
事件	2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, 中國持續時間: 18 10月 2004 → 21 10月 2004

Conference

Conference	2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
國家/地區	中國
城市	Beijing
期間	18/10/04 → 21/10/04

UN SDG

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10.1109/ICSICT.2004.1434952

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Zhu, S., Chen, J., Yu, H. Y., Whang, S. J., Chen, J. H., Shen, C., Li, M. F., Lee, S. J., Zhu, C., Chan, D. S. H., Du, A., Tung, C. H., Singh, J., Chin, A., & Kwong, D. L. (2004). Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes. 53-56. 論文發表於 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, 中國. https://doi.org/10.1109/ICSICT.2004.1434952

@conference{5b390a12e1144a309183bcf0a35c7782,

title = "Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes",

abstract = "Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO 2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of I on ∼10 7-10 8 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi 2-x silicide have also demonstrated a very promising characteristic with a recorded high I on/I off radio of∼ 10 7 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.",

author = "Shiyang Zhu and Jingde Chen and Yu, \{H. Y.\} and Whang, \{S. J.\} and Chen, \{J. H.\} and C. Shen and Li, \{M. F.\} and Lee, \{S. J.\} and Chunxiang Zhu and Chan, \{D. S.H.\} and Anyan Du and Tung, \{C. H.\} and Jagar Singh and Albert Chin and Kwong, \{D. L.\}",

year = "2004",

month = oct,

doi = "10.1109/ICSICT.2004.1434952",

language = "English",

pages = "53--56",

note = "2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 ; Conference date: 18-10-2004 Through 21-10-2004",

}

Zhu, S, Chen, J, Yu, HY, Whang, SJ, Chen, JH, Shen, C, Li, MF, Lee, SJ, Zhu, C, Chan, DSH, Du, A, Tung, CH, Singh, J, Chin, A & Kwong, DL 2004, 'Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes', 論文發表於 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, 中國, 18/10/04 - 21/10/04 頁 53-56. https://doi.org/10.1109/ICSICT.2004.1434952

TY - CONF

T1 - Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

AU - Zhu, Shiyang

AU - Chen, Jingde

AU - Yu, H. Y.

AU - Whang, S. J.

AU - Chen, J. H.

AU - Shen, C.

AU - Li, M. F.

AU - Lee, S. J.

AU - Zhu, Chunxiang

AU - Chan, D. S.H.

AU - Du, Anyan

AU - Tung, C. H.

AU - Singh, Jagar

AU - Chin, Albert

AU - Kwong, D. L.

PY - 2004/10

Y1 - 2004/10

N2 - Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO 2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of I on ∼10 7-10 8 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi 2-x silicide have also demonstrated a very promising characteristic with a recorded high I on/I off radio of∼ 10 7 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

AB - Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO 2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of I on ∼10 7-10 8 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi 2-x silicide have also demonstrated a very promising characteristic with a recorded high I on/I off radio of∼ 10 7 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

UR - https://www.scopus.com/pages/publications/21644481799

U2 - 10.1109/ICSICT.2004.1434952

DO - 10.1109/ICSICT.2004.1434952

M3 - Paper

AN - SCOPUS:21644481799

SP - 53

EP - 56

T2 - 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

Y2 - 18 October 2004 through 21 October 2004

ER -

Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

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