Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

Shiyang Zhu*, H. Y. Yu, S. J. Whang, J. H. Chen, Chen Shen, Chunxiang Zhu, S. J. Lee, M. F. Li, D. S.H. Chan, W. J. Yoo, Anyan Du, C. H. Tung, Jagar Singh, Albert Chin, D. L. Kwong

*此作品的通信作者

研究成果: Letter同行評審

103 引文 斯高帕斯(Scopus)

摘要

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff ∼ 107 - 108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, Ion/Ioff can reach ∼ 105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.

原文English
頁(從 - 到)268-270
頁數3
期刊IEEE Electron Device Letters
25
發行號5
DOIs
出版狀態Published - 1 五月 2004

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