Scaling of gate dielectric on Ge substrate

Yung Hsiang Chan, Bing-Yue Tsui

    研究成果: Conference contribution同行評審

    摘要

    Scaling of Hf-based and Zr-based gate dielectric stack on Ge is investigated. Effects of dielectric thickness and thermal budget on the MOS device characteristics are studied. Tradeoff among effective oxide thickness (EOT), leakage current density (JG), interface state density (Dit), and hysteresis are observed and discussed. With the same HfO2 and ZrO2 thickness, the ZrO2 samples exhibit lower Dit and smaller hysteresis but slightly higher JG. The crystallized ZrO2 exhibits the best JG-EOT performance. However, as the EOT becomes thinner than 0.8 nm, it is hard to lower Dit to 1×1012 eV-1cm-2. According to these results, novel techniques for Ge surface passivation and ZrO2 crystallization are required.

    原文English
    主出版物標題2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781509058051
    DOIs
    出版狀態Published - 7 6月 2017
    事件2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan
    持續時間: 24 4月 201727 4月 2017

    出版系列

    名字2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

    Conference

    Conference2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
    國家/地區Taiwan
    城市Hsinchu
    期間24/04/1727/04/17

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