Scaling Limitations of Line TFETs at Sub-8-nm Technology Node

Narasimhulu Thoti, Yiming Li*, Sekhar Reddy Kola

*此作品的通信作者

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (tn) of n-epitaxial region, and source-to-drain length (LSDeff) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 1018 cm-3, an optimal tn as low (about 0.5 nm), and a LSDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all.

原文English
主出版物標題2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面82-83
頁數2
ISBN(電子)9781728142326
DOIs
出版狀態Published - 8月 2020
事件2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
持續時間: 10 8月 202013 8月 2020

出版系列

名字2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
國家/地區Taiwan
城市Hsinchu
期間10/08/2013/08/20

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