TY - GEN
T1 - Scaling Limitations of Line TFETs at Sub-8-nm Technology Node
AU - Thoti, Narasimhulu
AU - Li, Yiming
AU - Kola, Sekhar Reddy
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/8
Y1 - 2020/8
N2 - The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (tn) of n-epitaxial region, and source-to-drain length (LSDeff) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 1018 cm-3, an optimal tn as low (about 0.5 nm), and a LSDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all.
AB - The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (tn) of n-epitaxial region, and source-to-drain length (LSDeff) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 1018 cm-3, an optimal tn as low (about 0.5 nm), and a LSDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all.
UR - http://www.scopus.com/inward/record.url?scp=85093670020&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA48913.2020.9203648
DO - 10.1109/VLSI-TSA48913.2020.9203648
M3 - Conference contribution
AN - SCOPUS:85093670020
T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
SP - 82
EP - 83
BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Y2 - 10 August 2020 through 13 August 2020
ER -