Scaled contact length with low contact resistance in monolayer 2D channel transistors

Wen Chia Wu; Terry Y.T. Hung; D. Mahaveer Sathaiya; Dongxu Fan; Goutham Arutchelvan; Chen Feng Hsu; Sheng Kai Su; Ang Sheng Chou; Edward Chen; Weisheng Li; Zhihao Yu; Hao Qiu; Ying Mei Yang; Kuang I. Lin; Yun Yang Shen; Wen Hao Chang; San Lin Liew; Vincent Hou; Jin Cai; Chung Cheng Wu; Jeff Wu; H. S. Philip Wong; Xinran Wang; Chao Hsin Chien; Chao Ching Cheng; Iuliana P. Radu

doi:10.23919/VLSITechnologyandCir57934.2023.10185408

Scaled contact length with low contact resistance in monolayer 2D channel transistors

Wen Chia Wu, Terry Y.T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen Feng Hsu, Sheng Kai Su, Ang Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying Mei Yang, Kuang I. Lin, Yun Yang Shen, Wen Hao Chang, San Lin Liew, Vincent Hou, Jin Cai, Chung Cheng WuJeff Wu, H. S. Philip Wong, Xinran Wang^*, Chao Hsin Chien^*, Chao Ching Cheng, Iuliana P. Radu^*

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

4 引文斯高帕斯（Scopus）

摘要

Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS2.

原文	English
主出版物標題	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185408
出版狀態	Published - 2023
事件	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, 日本持續時間: 11 6月 2023 → 16 6月 2023

出版系列

名字	Digest of Technical Papers - Symposium on VLSI Technology
卷	2023-June
ISSN（列印）	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
國家/地區	日本
城市	Kyoto
期間	11/06/23 → 16/06/23

存取文件

10.23919/VLSITechnologyandCir57934.2023.10185408

其它文件與鏈接

Link to publication in Scopus

引用此

Wu, W. C., Hung, T. Y. T., Sathaiya, D. M., Fan, D., Arutchelvan, G., Hsu, C. F., Su, S. K., Chou, A. S., Chen, E., Li, W., Yu, Z., Qiu, H., Yang, Y. M., Lin, K. I., Shen, Y. Y., Chang, W. H., Liew, S. L., Hou, V., Cai, J., ... Radu, I. P. (2023). Scaled contact length with low contact resistance in monolayer 2D channel transistors. 於 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185408

@inproceedings{faf519e6b22548bd941318ce8c6bb6d9,

title = "Scaled contact length with low contact resistance in monolayer 2D channel transistors",

abstract = "Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS2.",

author = "Wu, {Wen Chia} and Hung, {Terry Y.T.} and Sathaiya, {D. Mahaveer} and Dongxu Fan and Goutham Arutchelvan and Hsu, {Chen Feng} and Su, {Sheng Kai} and Chou, {Ang Sheng} and Edward Chen and Weisheng Li and Zhihao Yu and Hao Qiu and Yang, {Ying Mei} and Lin, {Kuang I.} and Shen, {Yun Yang} and Chang, {Wen Hao} and Liew, {San Lin} and Vincent Hou and Jin Cai and Wu, {Chung Cheng} and Jeff Wu and {Philip Wong}, {H. S.} and Xinran Wang and Chien, {Chao Hsin} and Cheng, {Chao Ching} and Radu, {Iuliana P.}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185408",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023",

address = "美國",

}

Wu, WC, Hung, TYT, Sathaiya, DM, Fan, D, Arutchelvan, G, Hsu, CF, Su, SK, Chou, AS, Chen, E, Li, W, Yu, Z, Qiu, H, Yang, YM, Lin, KI, Shen, YY, Chang, WH, Liew, SL, Hou, V, Cai, J, Wu, CC, Wu, J, Philip Wong, HS, Wang, X, Chien, CH, Cheng, CC & Radu, IP 2023, Scaled contact length with low contact resistance in monolayer 2D channel transistors. 於 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, 卷 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, 日本, 11/06/23. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185408

Scaled contact length with low contact resistance in monolayer 2D channel transistors. / Wu, Wen Chia; Hung, Terry Y.T.; Sathaiya, D. Mahaveer 等.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2023-June).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Scaled contact length with low contact resistance in monolayer 2D channel transistors

AU - Wu, Wen Chia

AU - Hung, Terry Y.T.

AU - Sathaiya, D. Mahaveer

AU - Fan, Dongxu

AU - Arutchelvan, Goutham

AU - Hsu, Chen Feng

AU - Su, Sheng Kai

AU - Chou, Ang Sheng

AU - Chen, Edward

AU - Li, Weisheng

AU - Yu, Zhihao

AU - Qiu, Hao

AU - Yang, Ying Mei

AU - Lin, Kuang I.

AU - Shen, Yun Yang

AU - Chang, Wen Hao

AU - Liew, San Lin

AU - Hou, Vincent

AU - Cai, Jin

AU - Wu, Chung Cheng

AU - Wu, Jeff

AU - Philip Wong, H. S.

AU - Wang, Xinran

AU - Chien, Chao Hsin

AU - Cheng, Chao Ching

AU - Radu, Iuliana P.

PY - 2023

Y1 - 2023

N2 - Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS2.

AB - Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS2.

UR - http://www.scopus.com/inward/record.url?scp=85167587824&partnerID=8YFLogxK

U2 - 10.23919/VLSITechnologyandCir57934.2023.10185408

DO - 10.23919/VLSITechnologyandCir57934.2023.10185408

M3 - Conference contribution

AN - SCOPUS:85167587824

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

Y2 - 11 June 2023 through 16 June 2023

ER -

Wu WC, Hung TYT, Sathaiya DM, Fan D, Arutchelvan G, Hsu CF 等. Scaled contact length with low contact resistance in monolayer 2D channel transistors. 於 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185408

Scaled contact length with low contact resistance in monolayer 2D channel transistors

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Conference

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