Scaled contact length with low contact resistance in monolayer 2D channel transistors

Wen Chia Wu, Terry Y.T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen Feng Hsu, Sheng Kai Su, Ang Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying Mei Yang, Kuang I. Lin, Yun Yang Shen, Wen Hao Chang, San Lin Liew, Vincent Hou, Jin Cai, Chung Cheng WuJeff Wu, H. S. Philip Wong, Xinran Wang*, Chao Hsin Chien*, Chao Ching Cheng, Iuliana P. Radu*

*此作品的通信作者

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS2.

原文English
主出版物標題2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9784863488069
DOIs
出版狀態Published - 2023
事件2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
持續時間: 11 6月 202316 6月 2023

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2023-June
ISSN(列印)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
國家/地區Japan
城市Kyoto
期間11/06/2316/06/23

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