Scalable mutli-layer barrier synchronization on NoC

Yu Lun Tseng, Kun Hua Huang, Bo-Cheng Lai

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32×32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 31 5月 2016
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 25 4月 201627 4月 2016

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家/地區Taiwan
城市Hsinchu
期間25/04/1627/04/16

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