Rule Generation for Classifying SLT Failed Parts

Ho Chieh Hsu, Cheng Che Lu, Shih Wei Wang, Kelly Jones, Kai Chiang Wu, Mango C.T. Chao

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)


System-level test (SLT) has recently gained visibility when integrated circuits become harder and harder to be fully tested due to increasing transistor density and circuit design complexity. Albeit SLT is effective for reducing test escapes, little diagnostic information can be obtained for product improvement. In this paper, we propose an unsupervised learning (UL) method to resolve the aforementioned issue by discovering correlative, potentially systematic defects during the SLT phase. Toward this end, HDBSCAN [1] is used for clustering SLT failed devices in a low-dimensional space created by UMAP [2]. Decision trees are subsequently applied to explain the HDBSCAN results based on generating explainable quantitative rules, e.g., inequality constraints, providing domain experts additional information for advanced diagnosis. Experiments on industrial data demonstrate that the proposed methodology can effectively cluster SLT failed devices and then explain the clustering results with a promising accuracy of above 90%. Our methodology is also scalable and fast, requiring two to five orders of magnitude lower runtime than the method presented in [3].

主出版物標題Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022
發行者IEEE Computer Society
出版狀態Published - 2022
事件40th IEEE VLSI Test Symposium, VTS 2022 - Virtual, Online, United States
持續時間: 25 4月 202227 4月 2022


名字Proceedings of the IEEE VLSI Test Symposium


Conference40th IEEE VLSI Test Symposium, VTS 2022
國家/地區United States
城市Virtual, Online


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