ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays

Yi Hang Chen, Yang Chen, Juinn-Dar Huang

    研究成果: Conference contribution同行評審

    6 引文 斯高帕斯(Scopus)

    摘要

    The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.

    原文English
    主出版物標題2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781479962754
    DOIs
    出版狀態Published - 28 5月 2015
    事件2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
    持續時間: 27 4月 201529 4月 2015

    出版系列

    名字2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

    Conference

    Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
    國家/地區Taiwan
    城市Hsinchu
    期間27/04/1529/04/15

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