RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

Sang Lam; Hui Wan; Pin Su; Peter W. Wyatt; C. L. Chen; Ali M. Niknejad; Chen-Ming Hu; Ping K. Ko; Mansun Chan

doi:10.1109/LED.2003.810892

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

Sang Lam^*, Hui Wan, Pin Su, Peter W. Wyatt, C. L. Chen, Ali M. Niknejad, Chen-Ming Hu, Ping K. Ko, Mansun Chan

^*此作品的通信作者

研究成果: Letter › 同行評審

10 引文斯高帕斯（Scopus）

摘要

The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance R_G, the metal T-gate FD-SOI MOSFET achieves a higher f_max of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower f_T of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances C_gs and C_gd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

原文	English
頁（從 - 到）	251-253
頁數	3
期刊	Ieee Electron Device Letters
卷	24
發行號	4
DOIs	https://doi.org/10.1109/LED.2003.810892
出版狀態	Published - 1 4月 2003

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10.1109/LED.2003.810892

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title = "RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology",

abstract = "The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance RG, the metal T-gate FD-SOI MOSFET achieves a higher fmax of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower fT of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances Cgs and Cgd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.",

keywords = "Fully-depleted SOI MOSFET, Metal gate, RF CMOS, T-gate structure",

author = "Sang Lam and Hui Wan and Pin Su and Wyatt, {Peter W.} and Chen, {C. L.} and Niknejad, {Ali M.} and Chen-Ming Hu and Ko, {Ping K.} and Mansun Chan",

year = "2003",

month = apr,

day = "1",

doi = "10.1109/LED.2003.810892",

language = "English",

volume = "24",

pages = "251--253",

journal = "Ieee Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

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TY - JOUR

T1 - RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

AU - Lam, Sang

AU - Wan, Hui

AU - Su, Pin

AU - Wyatt, Peter W.

AU - Chen, C. L.

AU - Niknejad, Ali M.

AU - Hu, Chen-Ming

AU - Ko, Ping K.

AU - Chan, Mansun

PY - 2003/4/1

Y1 - 2003/4/1

N2 - The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance RG, the metal T-gate FD-SOI MOSFET achieves a higher fmax of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower fT of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances Cgs and Cgd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

AB - The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance RG, the metal T-gate FD-SOI MOSFET achieves a higher fmax of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower fT of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances Cgs and Cgd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

KW - Fully-depleted SOI MOSFET

KW - Metal gate

KW - RF CMOS

KW - T-gate structure

UR - http://www.scopus.com/inward/record.url?scp=0038781379&partnerID=8YFLogxK

U2 - 10.1109/LED.2003.810892

DO - 10.1109/LED.2003.810892

M3 - Letter

AN - SCOPUS:0038781379

SN - 0741-3106

VL - 24

SP - 251

EP - 253

JO - Ieee Electron Device Letters

JF - Ieee Electron Device Letters

IS - 4

ER -

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

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