Research of electroplating and electroless plating for low temperature bonding in 3D heterogeneous integration

Yu Chen Hu, Yao Jen Chang, Chun Shen Wu, Yung Mao Cheng, Wei Jen Chen, Kuan Neng Chen

研究成果: Conference contribution同行評審

摘要

In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270°C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn μ-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 μm bump pitch, 40 μm diameter of Cu/Sn μ-bump and 50 μm diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.

原文English
主出版物標題2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference
主出版物子標題Challenges of Change - Shaping the Future, IMPACT 2014 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面290-293
頁數4
ISBN(電子)9781479977277
DOIs
出版狀態Published - 1 一月 2014
事件9th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2014 - Taipei, Taiwan
持續時間: 22 十月 201424 十月 2014

出版系列

名字2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference: Challenges of Change - Shaping the Future, IMPACT 2014 - Proceedings

Conference

Conference9th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2014
國家/地區Taiwan
城市Taipei
期間22/10/1424/10/14

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