TY - JOUR
T1 - REMAP+
T2 - An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory
AU - Lai, Bo Cheng
AU - Chen, Bo Ya
AU - Chen, Bo En
AU - Hsin, Yi Da
PY - 2020/3
Y1 - 2020/3
N2 - Supporting multiple write ports is one of the main challenges when designing algorithmic multiported memory (AMM). AMM supports concurrent accesses by cooperating multiple, low-complexity memory modules together with logical operations. When scaling the number of write ports, the nontable-based approaches quadratically increase the number of memory modules, whereas the table-based approaches tend to introduce complex lookup tables and access handling logics. In this article, we introduce REMAP+, an efficient banking architecture to support multiple writes. We optimize the pipeline of REMAP+ to achieve high access bandwidth and more efficient table access. We also exploit the structured architecture of REMAP+ and propose a systematic design flow to automate the scaling of write ports and optimization of banking. Comprehensive analysis is presented to reveal the insight into design features and concerns. Based on extensive experiments, we have shown that REMAP+ outperforms the existing write schemes (XOR, live value table (LVT), and REMAP) with higher bandwidth (49%, 50%, 18%), lower energy (28%, 49%, 54%), and smaller area (43%, 37%, 35%).
AB - Supporting multiple write ports is one of the main challenges when designing algorithmic multiported memory (AMM). AMM supports concurrent accesses by cooperating multiple, low-complexity memory modules together with logical operations. When scaling the number of write ports, the nontable-based approaches quadratically increase the number of memory modules, whereas the table-based approaches tend to introduce complex lookup tables and access handling logics. In this article, we introduce REMAP+, an efficient banking architecture to support multiple writes. We optimize the pipeline of REMAP+ to achieve high access bandwidth and more efficient table access. We also exploit the structured architecture of REMAP+ and propose a systematic design flow to automate the scaling of write ports and optimization of banking. Comprehensive analysis is presented to reveal the insight into design features and concerns. Based on extensive experiments, we have shown that REMAP+ outperforms the existing write schemes (XOR, live value table (LVT), and REMAP) with higher bandwidth (49%, 50%, 18%), lower energy (28%, 49%, 54%), and smaller area (43%, 37%, 35%).
KW - Algorithmic multiported memory (AMM)
KW - banking structure
KW - memory architecture
KW - multiple writes
UR - http://www.scopus.com/inward/record.url?scp=85080867388&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2019.2957455
DO - 10.1109/TVLSI.2019.2957455
M3 - Article
AN - SCOPUS:85080867388
SN - 1063-8210
VL - 28
SP - 660
EP - 671
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
M1 - 8939326
ER -