The object of this paper is to propose new architecture which can reduce the number of processing elements for parallel local image processing under the premise of real-time performance. For large-sized local image processing, this architecture will save much space as it is suitable for being designed into VLSI chip. For example, the traditional parallel architecture will use 9 PEs for a 3X3 convolution, while the Reduced Processing Element Architecture (RPEA) only requires 2 PEs to achieve the real-time performance.
|頁（從 - 到）
|Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an
|Published - 1 1月 1987