TY - GEN
T1 - Record Transconductance in Leff30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2Superlattice Gate Stack
AU - Wang, L. C.
AU - Li, W.
AU - Shanker, N.
AU - Cheema, S. S.
AU - Hsu, S. L.
AU - Volkman, S.
AU - Sikder, U.
AU - Garg, C.
AU - Park, J. H.
AU - Liao, Y. H.
AU - Lin, Y. K.
AU - Hu, C.
AU - Salahuddin, S.
N1 - Publisher Copyright:
© 2023 JSAP.
PY - 2023
Y1 - 2023
N2 - We demonstrate short channel, extremely thin SOI (ETSOI, 6< nm), replacement gate nFETs down to effective gate length (Leff)∼ 30nm with low equivalent oxide thickness (EOT) negative capacitance (NC) HfO2-ZrO2 superlattice (HZH) gate stack [1-2]. Inversion capacitance measurement shows an EOT of 7 Å, which is 2.5-Å lower than typical industry HfO2 dielectrics. The transistors show record intrinsic transconductance (gmi)-2.11mS/mum, rivaling what is achieved in much shorter channel length (18nm) commercial devices such as 22FDX® technology. Importantly, the gm-Lg scaling trends deviate from industry benchmarks, showing that much larger gmi is achievable at the same channel length. Despite significantly worse series resistance, the devices show favorable performance in IonvsI on/Ioff tradeoff, providing larger I on and lower I off compared to industrial benchmarks of similar channel length.
AB - We demonstrate short channel, extremely thin SOI (ETSOI, 6< nm), replacement gate nFETs down to effective gate length (Leff)∼ 30nm with low equivalent oxide thickness (EOT) negative capacitance (NC) HfO2-ZrO2 superlattice (HZH) gate stack [1-2]. Inversion capacitance measurement shows an EOT of 7 Å, which is 2.5-Å lower than typical industry HfO2 dielectrics. The transistors show record intrinsic transconductance (gmi)-2.11mS/mum, rivaling what is achieved in much shorter channel length (18nm) commercial devices such as 22FDX® technology. Importantly, the gm-Lg scaling trends deviate from industry benchmarks, showing that much larger gmi is achievable at the same channel length. Despite significantly worse series resistance, the devices show favorable performance in IonvsI on/Ioff tradeoff, providing larger I on and lower I off compared to industrial benchmarks of similar channel length.
UR - http://www.scopus.com/inward/record.url?scp=85167562293&partnerID=8YFLogxK
U2 - 10.23919/VLSITechnologyandCir57934.2023.10185436
DO - 10.23919/VLSITechnologyandCir57934.2023.10185436
M3 - Conference contribution
AN - SCOPUS:85167562293
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Y2 - 11 June 2023 through 16 June 2023
ER -