Reconfigurable low power MPEG-4 texture decoder IP design

Chien Chang Lin*, Hsiu Cheng Chang, Kuan Hung Chen, Jiun-In  Guo

*此作品的通信作者

研究成果同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35μm CMOS technology.

原文English
頁面153-156
頁數4
DOIs
出版狀態Published - 12月 2004
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, 台灣
持續時間: 6 12月 20049 12月 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區台灣
城市Tainan
期間6/12/049/12/04

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