Realization of a systematic bit-wise decomposition metric

Chia Wei Chang*, Po-Ning Chen, Yunghsiang S. Han

*此作品的通信作者

研究成果: Paper同行評審

摘要

In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.

原文English
頁面1065-1068
頁數4
DOIs
出版狀態Published - 6 12月 2004
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 6 12月 20049 12月 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區Taiwan
城市Tainan
期間6/12/049/12/04

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