Methods are presented to reduce both the onboard storage volume and transmission-rate requirement for NASA's two high-rate instruments the HIRIS high-resolution imaging spectrometer and the synthetic-Aperture radar (SAR) to be flown as research facility instruments on the NASA earth observing system (EOS) polar-orbiting platforms. A distortion-free coding scheme capable of providing a factor of three-to-one in data compression is described. The data compression scheme is a variant of the block adaptive rate controlled (BARC) method. Special emphasis is placed on the changes made to accommodate the VLSI design approach. A conceptual design utilizing the VLSI parallel/pipelined architecture capable of meeting real-time processing requirement is provided. The architecture consists of a parallel array of VLSI compressor modules with each module built on a single customized VLSI chip. It is capable of achieving throughput rate at one gigabit per second.
|頁（從 - 到）||155-160|
|期刊||EASCON Record: IEEE Electronics and Aerospace Systems Convention|
|出版狀態||Published - 1 12月 1987|
|事件||EASCON Rec 20th, Annu Electron and Aerosp Syst Conf - Technol for Space Leadership Conf Proc - Washington, DC, USA|
持續時間: 14 10月 1987 → 16 10月 1987