Random pattern generation for post-silicon validation of DDR3 SDRAM

Hao Yu Yang, Shih Hua Kuo, Tzu Hsuan Huang, Chi Hung Chen, Chris Lin, Chia-Tso Chao

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)


Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.

主出版物標題Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015
發行者IEEE Computer Society
出版狀態Published - 1 6月 2015
事件2015 33rd IEEE VLSI Test Symposium, VTS 2015 - Napa, United States
持續時間: 27 4月 201529 4月 2015


名字Proceedings of the IEEE VLSI Test Symposium


Conference2015 33rd IEEE VLSI Test Symposium, VTS 2015
國家/地區United States


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