Random Interface-traps-induced electrical characteristic fluctuation in 16-nm-gate high-κ/metal gate complementary metal-oxide-semiconductor device and inverter circuit

This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-κ/metal gate (HKMG) metal-oxide-semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-κ/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO ₂/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device's inversion layer cannot effectively screen potential's variation; thus, devices still have noticeable fluctuation of gate capacitance (C _G) under high gate bias. The cutoff frequency decreases as increasing the number of ITs owing to the decreasing transconductance and increasing C _G. Decreasing on-state current and increasing C _G further result in increasing intrinsic gate delay time (τ) when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and τ above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal-oxide-semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs' fluctuations are increased due to the more sources of fluctuation at HfO ₂/Si interface of HKMG devices.