QAM/VSB dual mode equalizer design and implementation

C. F. Wu, M. T. Shiue, C. C. Huang, Shyh-Jye Jou

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

A novel architecture for dual mode equalizer of CATV modem is proposed. It is not only suitable for quadrature amplitude modulation (QAM) system but also suitable for vestigial sideband modulation (VSB) system. This dual mode equalizer consists of fractionally spaced equalizer (FSE) and decision feedback equalizer (DFE) architecture. The FSE has 12 taps filter and uses sign-delayed LMS (SDLMS) coefficients updating methodology with "stop-and-go" algorithm. The DFE has 13 taps filter and uses sign-delayed LMS coefficients updating methodology. Also, a multi-state control scheme, a multi-slice slicer and a multi-step size are used to speed up the convergence of system. The system data rate is 5 MBaud and the maximum internal operation clock of the equalizer is 102 MHz. The chip is implemented with 0.6 μm CMOS TSMC 1P3M technology. The core area is 4044 μm×4044 μm and consumes 1.938 W power consumption.

原文English
主出版物標題AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
發行者Institute of Electrical and Electronics Engineers Inc.
頁面323-326
頁數4
ISBN(列印)0780357051, 9780780357051
DOIs
出版狀態Published - 1 1月 1999
事件1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
持續時間: 23 8月 199925 8月 1999

出版系列

名字AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
國家/地區Korea, Republic of
城市Seoul
期間23/08/9925/08/99

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