TY - JOUR
T1 - Prototype IC with WDDL and differential routing - DPA resistance assessment
AU - Tiri, Kris
AU - Hwang, David
AU - Hodjat, Alireza
AU - Lai, Bo-Cheng
AU - Yang, Shenglin
AU - Schaumont, Patrick
AU - Verbauwhede, Ingrid
PY - 2005/11/4
Y1 - 2005/11/4
N2 - Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.
AB - Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.
KW - Countermeasure
KW - Differential power analysis (DPA)
KW - Differential routing
KW - Dual rail with precharge
KW - Parasitic capacitance matching
KW - Side-channel attack (SCA)
KW - Wave dynamic differential logic (WDDL)
UR - http://www.scopus.com/inward/record.url?scp=27244438768&partnerID=8YFLogxK
U2 - 10.1007/11545262_26
DO - 10.1007/11545262_26
M3 - Conference article
AN - SCOPUS:27244438768
SN - 0302-9743
VL - 3659
SP - 354
EP - 365
JO - Lecture Notes in Computer Science
JF - Lecture Notes in Computer Science
T2 - 7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005
Y2 - 29 August 2005 through 1 September 2005
ER -