Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

C. H. Ge; C. C. Lin; C. H. Ko; C. C. Huang; Y. C. Huang; B. W. Chan; B. C. Perng; C. C. Sheu; P. Y. Tsai; L. G. Yao; C. L. Wu; T. L. Lee; C. J. Chen; C. T. Wang; S. C. Lin; Y. C. Yeo; Chen-Ming Hu

doi:10.1109/IEDM.2003.1269169

Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

C. H. Ge^*, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

114 引文斯高帕斯（Scopus）

摘要

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, suicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

原文	English
頁（從 - 到）	73-76
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2003.1269169
出版狀態	Published - 1 12月 2003
事件	IEEE International Electron Devices Meeting - Washington, DC, 美國持續時間: 8 12月 2003 → 10 12月 2003

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Ge, C. H., Lin, C. C., Ko, C. H., Huang, C. C., Huang, Y. C., Chan, B. W., Perng, B. C., Sheu, C. C., Tsai, P. Y., Yao, L. G., Wu, C. L., Lee, T. L., Chen, C. J., Wang, C. T., Lin, S. C., Yeo, Y. C., & Hu, C.-M. (2003). Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering. Technical Digest - International Electron Devices Meeting, 73-76. https://doi.org/10.1109/IEDM.2003.1269169

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title = "Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering",

abstract = "We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, suicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.",

author = "Ge, {C. H.} and Lin, {C. C.} and Ko, {C. H.} and Huang, {C. C.} and Huang, {Y. C.} and Chan, {B. W.} and Perng, {B. C.} and Sheu, {C. C.} and Tsai, {P. Y.} and Yao, {L. G.} and Wu, {C. L.} and Lee, {T. L.} and Chen, {C. J.} and Wang, {C. T.} and Lin, {S. C.} and Yeo, {Y. C.} and Chen-Ming Hu",

year = "2003",

month = dec,

day = "1",

doi = "10.1109/IEDM.2003.1269169",

language = "English",

pages = "73--76",

journal = "Technical Digest - International Electron Devices Meeting",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting ; Conference date: 08-12-2003 Through 10-12-2003",

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TY - JOUR

T1 - Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

AU - Ge, C. H.

AU - Lin, C. C.

AU - Ko, C. H.

AU - Huang, C. C.

AU - Huang, Y. C.

AU - Chan, B. W.

AU - Perng, B. C.

AU - Sheu, C. C.

AU - Tsai, P. Y.

AU - Yao, L. G.

AU - Wu, C. L.

AU - Lee, T. L.

AU - Chen, C. J.

AU - Wang, C. T.

AU - Lin, S. C.

AU - Yeo, Y. C.

AU - Hu, Chen-Ming

PY - 2003/12/1

Y1 - 2003/12/1

N2 - We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, suicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

AB - We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, suicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

UR - http://www.scopus.com/inward/record.url?scp=0842288292&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2003.1269169

DO - 10.1109/IEDM.2003.1269169

M3 - Conference article

AN - SCOPUS:0842288292

SN - 0163-1918

SP - 73

EP - 76

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting

Y2 - 8 December 2003 through 10 December 2003

ER -

Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

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