@inproceedings{ee9850611e8f43ada6be2ef9e3aa5f1e,
title = "Process and Structure Considerations for the Post FinFET Era",
abstract = "Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.",
keywords = "CMOS, FinFET, nanosheet, nanowire",
author = "Chun-Jung Su and Sung, {Po Jung} and Kao, {Kuo Hsing} and Lee, {Yao Jen} and Wu, {Wen Fa} and Wen-Kuan Yeh",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 ; Conference date: 13-06-2020 Through 14-06-2020",
year = "2020",
month = jun,
doi = "10.1109/SNW50361.2020.9131422",
language = "English",
series = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "13--14",
booktitle = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",
address = "美國",
}