Process and Structure Considerations for the Post FinFET Era

Chun-Jung Su*, Po Jung Sung, Kuo Hsing Kao, Yao Jen Lee, Wen Fa Wu, Wen-Kuan Yeh

*此作品的通信作者

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

原文English
主出版物標題2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面13-14
頁數2
ISBN(電子)9781728197357
DOIs
出版狀態Published - 6月 2020
事件2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States
持續時間: 13 6月 202014 6月 2020

出版系列

名字2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
國家/地區United States
城市Honolulu
期間13/06/2014/06/20

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