Prioritization of key in-line process parameters for electrical characteristic optimization of high-k metal gate bulk FinFET devices

Ping Husn Su, Yi-ming Li

研究成果: Conference contribution同行評審

摘要

This work reports a novel method to discovery and optimize key fabrication in-line process of 16-nm HKMG bulk FinFET to improve device's performance and variability. The sensitivity analysis is utilized to prioritize key in-line process parameters which significantly boost device's performance and effectively reduce its variations. To extract hidden correlations among complex and a large number of in-line process parameters, data mining technique is applied to highlight and group associated in-line process parameters. The source of variations of in-line process parameters in each group is revealed and the optimized solution is proposed to reduce its sensitivity to devices' fluctuation. Results show the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant are grouped to the same cluster and significantly affect the threshold voltage (Vt,sat), the on-state current (Id,sat) and the off-state current (Id,off), but the key variation source of these parameters is the thickness of the dual gate-spacer. By replacing dual spacers with single spacers, the fluctuation of threshold voltage is 30% dropped.

原文English
主出版物標題e-Manufacturing and Design Collaboration Symposium 2016, eMDC 2016 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9789869171526
出版狀態Published - 20 十月 2016
事件2016 e-Manufacturing and Design Collaboration Symposium, eMDC 2016 - Hsinchu, Taiwan
持續時間: 9 九月 2016 → …

出版系列

名字e-Manufacturing and Design Collaboration Symposium 2016, eMDC 2016 - Proceedings

Conference

Conference2016 e-Manufacturing and Design Collaboration Symposium, eMDC 2016
國家/地區Taiwan
城市Hsinchu
期間9/09/16 → …

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