Predicting Vt mean and variance from parallel Id measurement with model-fitting technique

Chih Ying Tsai, Kao Chi Lee, Chien Hsueh Lin, Sung Chu Yu, Wen Rong Liau, Alex Chun Liang Hou, Ying Yen Chen, Chun Yi Kuo, Jih Nung Lee, Chia-Tso Chao

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

To measure the variation of device Vt requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based on only the combined Id measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vt mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Id measurement per DUT.

原文English
主出版物標題Proceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016
發行者IEEE Computer Society
ISBN(電子)9781467384544
DOIs
出版狀態Published - 23 5月 2016
事件34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States
持續時間: 25 4月 201627 4月 2016

出版系列

名字Proceedings of the IEEE VLSI Test Symposium
2016-May

Conference

Conference34th IEEE VLSI Test Symposium, VTS 2016
國家/地區United States
城市Las Vegas
期間25/04/1627/04/16

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