Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics

Shu Yung Bin, Shih Feng Lin, Ya Ching Cheng, Wen Rong Liau, Alex Hou, Chia-Tso Chao

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

An SRAM-array test structure provides the capability of directly measuring the characteristics of each transistor and the read/write metrics for each static random access memory (SRAM) cell in the array. However, the total test time of measuring the read/write metrics takes longer than that of measuring each transistor's characteristics. This paper presents a model-fitting framework to predict the average read/write metrics of the SRAM cells in a lithography shot using only the measured transistor characteristics. The proposed framework is validated through the measurement result of 4750 samples of a 128-bit SRAM-array test structure implemented in a United Microelectronics Corporation 28-nm process technology. The experimental results show that the learned models can achieve at least 97.77% R -square on fitting the shot-level read static noise margin, write margin, and read current based on 2375-sample testing data.

原文English
文章編號7089307
頁(從 - 到)625-637
頁數13
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
24
發行號2
DOIs
出版狀態Published - 2月 2016

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