Pre-RTL DNN Hardware Evaluator with Fused Layer Support

Chih Chyau Yang, Tian Sheuan Chang

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

With the popularity of the deep neural network (DNN), hardware accelerators are demanded for real time execution. However, lengthy design process and fast evolving DNN models make hardware evaluation hard to meet the time to market need. This paper proposes a pre-RTL DNN hardware evaluator that supports conventional layer-by-layer processing as well as the fused layer processing for low external bandwidth requirement. The evaluator supports two state-of-The-Art accelerator architectures and finds the best hardware and layer fusion group. The experimental results show the layer fusion scheme can achieve 55.6% memory bandwidth reduction, 36.7% latency improvement and 49.2% energy reduction compared with layer-by-layer operation.

原文English
主出版物標題Proceedings - International SoC Design Conference 2021, ISOCC 2021
發行者Institute of Electrical and Electronics Engineers Inc.
頁面83-84
頁數2
ISBN(電子)9781665401746
DOIs
出版狀態Published - 2021
事件18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, 韓國
持續時間: 6 10月 20219 10月 2021

出版系列

名字Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference18th International System-on-Chip Design Conference, ISOCC 2021
國家/地區韓國
城市Jeju Island
期間6/10/219/10/21

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