TY - GEN
T1 - Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process
AU - Altolaguirre, Federico A.
AU - Ker, Ming-Dou
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/9/23
Y1 - 2014/9/23
N2 - SCR is the preferred ESD protection device in nanoscale CMOS technologies due to the better area efficiency compared the BIGFET, virtually no leakage current and smaller capacitance. The main drawback of the SCR is the slow turn-on speed, which is solved by adding dummy gates to block the STI formations inside the SCR structure. This work demonstrates that the dummy gate inside the SCR can be effectively used as an embedded trigger transistor, eliminating the need of an external trigger transistor in the ESD protection circuit and so further reducing silicon area and standby leakage current.
AB - SCR is the preferred ESD protection device in nanoscale CMOS technologies due to the better area efficiency compared the BIGFET, virtually no leakage current and smaller capacitance. The main drawback of the SCR is the slow turn-on speed, which is solved by adding dummy gates to block the STI formations inside the SCR structure. This work demonstrates that the dummy gate inside the SCR can be effectively used as an embedded trigger transistor, eliminating the need of an external trigger transistor in the ESD protection circuit and so further reducing silicon area and standby leakage current.
UR - http://www.scopus.com/inward/record.url?scp=84908472251&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2014.6908399
DO - 10.1109/MWSCAS.2014.6908399
M3 - Conference contribution
AN - SCOPUS:84908472251
T3 - Midwest Symposium on Circuits and Systems
SP - 250
EP - 253
BT - 2014 IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014
Y2 - 3 August 2014 through 6 August 2014
ER -