Power optimization for clock network with clock gate cloning and flip-flop merging

Shih Chuan Lo, Chih Cheng Hsu, Po-Hung Lin

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective techniques for low power clock network design. Some previous works had proposed to optimize clock network with either CGs or MBFFs, but none of them simultaneously considers both CGs and MBFFs during clock network optimization. Although CGs and MBFFs can be optimized separately, the resulting dynamic power may not be optimal. This paper presents the first problem formulation in the literature for gated clock network optimization with simultaneous CG cloning and FF merging. To effectively solve the problem, a novel optimization flow consisting of MBFF-aware CG cloning, CG-based FF merging, and MBFF and CG placement optimization is introduced. Experimental results show that the proposed flow results in better dynamic power and clock wirelength compared with other flows which optimize gated clock network with CGs and MBFFs separately.

原文English
主出版物標題ISPD 2014 - Proceedings of the 2014 ACM International Symposium on Physical Design
發行者Association for Computing Machinery
頁面77-83
頁數7
ISBN(列印)9781450325929
DOIs
出版狀態Published - 1 一月 2014
事件2014 ACM International Symposium on Physical Design, ISPD 2014 - Petaluma, CA, United States
持續時間: 30 三月 20142 四月 2014

出版系列

名字Proceedings of the International Symposium on Physical Design

Conference

Conference2014 ACM International Symposium on Physical Design, ISPD 2014
國家/地區United States
城市Petaluma, CA
期間30/03/142/04/14

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