Power-efficient cyclic voltammetric electrochemical sensing readout circuitry with current-reducer ramp waveform generation

Yi Chia Chen, Shao Yung Lu, Yu-Te Liao

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper presents an electrochemical sensing chip with an integrated current-reducer pattern generator and a low-noise chopper-stabilization potentiostat circuit. The pattern generator, utilizing the current reducer technique and pseudo resistors, creates a sub-Hz ramp signal for the cyclic voltammetric measurement without large-size passive components. The proposed design adopts a chopper-stabilization potentiostat and time-based converter to reduce the amplitude noise effects. The design is fabricated using a 0.18-μm CMOS process and achieves a 41pA current resolution in the current range of ± 5μA while maintaining the R2 linearity of 0.998. The power consumption of the design is 16μW when a 5μA sensing current is detected. The power efficiency of the readout interface is 0.31 and the sensing current dynamic range is 108dB. The design is fully integrated into a single chip.

原文English
主出版物標題2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728103976
DOIs
出版狀態Published - 1 1月 2019
事件2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, 日本
持續時間: 26 5月 201929 5月 2019

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2019-May
ISSN(列印)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
國家/地區日本
城市Sapporo
期間26/05/1929/05/19

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