As supply voltage keeps scaling, the timing of an IC becomes more sensitive to the IR-drop of its power distribution network (PDN). In conventional timing signoff, designers assign a fixed voltage to all cells during the entire analysis process, which leads to over-design since the exact voltages at most cells are larger than the assigned value for timing analysis. To reflect the actual timing of a circuit, IR-drop aware timing analysis should be applied for timing signoff. This paper proposes a framework that can automatically generate a refined PDN for optimizing IR-drop aware timing based on a given initial PDN and cell placement. Our framework uses two novel timing-cost indexes to measure the impact of a PDN on IR-drop aware timing and a novel dynamic-programming based algorithm to obtain an optimal timing-driven PDN while efficiently handling the discontinuity of power rails caused by macros. The experiments based on various 28nm industrial designs demonstrate that our framework can always generate a PDN resulting in less worst-case negative slack, less total negative slack, and less timing-violating paths, compared to a previous work focusing on minimizing routing overhead. Our framework accesses all design information and makes all PDN changes through commercial EDA tools, and hence can be easily integrated into industrial design flows.
|IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
|Published - 2 11月 2020
|39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020 - Virtual, San Diego, United States
持續時間: 2 11月 2020 → 5 11月 2020