Power and substrate noise tolerance of configurable embedded memories in SoC

Meng Fan Chang*, Kuei-Ann Wen

*此作品的通信作者

    研究成果: Article同行評審

    4 引文 斯高帕斯(Scopus)

    摘要

    When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 μ m CMOS process are studied.

    原文English
    頁(從 - 到)81-91
    頁數11
    期刊Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
    41
    發行號1
    DOIs
    出版狀態Published - 1 8月 2005

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