Power and area reduction in multi-stage addition using operand segmentation

Ching Da Chan, Wei Chang Liu, Chia Hsiang Yang, Shyh-Jye Jou

    研究成果: Conference contribution同行評審

    摘要

    This paper presents an architectural technique to efficiently implement multi-stage additions through operand segmentation. Carry bypass is leveraged to break the dependency between the two segmented adders, reducing the delay of the critical path. This allows for power-and area-efficient hardware implementation due to the increased timing margin for architectural transformations at the cost of one extra clock cycle. Compared to existing segmented-adders, the proposed architecture has the least hardware overhead with near execution time. An accumulator and a 16-tap FIR filter are used to demonstrate the delay, power, and area improvements of the proposed technique. The synthesis results show that the delay is improved by up to 42% and 28.1%. Given the same timing constraint, the adder area is reduced by 27.4% and 12.4%.

    原文English
    主出版物標題2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
    DOIs
    出版狀態Published - 2013
    事件2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
    持續時間: 22 4月 201324 4月 2013

    出版系列

    名字2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

    Conference

    Conference2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
    國家/地區Taiwan
    城市Hsinchu
    期間22/04/1324/04/13

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