Post-placement power optimization with multi-bit flip-flops

Yao Tsung Chang*, Chih Cheng Hsu, Po-Hung Lin, Yu Wen Tsai, Sheng Fong Chen

*此作品的通信作者

研究成果: Conference contribution同行評審

51 引文 斯高帕斯(Scopus)

摘要

Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.

原文English
主出版物標題2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
頁面218-223
頁數6
DOIs
出版狀態Published - 1 十二月 2010
事件2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States
持續時間: 7 十一月 201011 十一月 2010

出版系列

名字IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN(列印)1092-3152

Conference

Conference2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
國家/地區United States
城市San Jose, CA
期間7/11/1011/11/10

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