Post-placement power optimization with multi-bit flip-flops

Po-Hung Lin*, Chih Cheng Hsu, Yao Tsung Chang

*此作品的通信作者

研究成果: Article同行評審

29 引文 斯高帕斯(Scopus)

摘要

Optimization for power is always one of the most important design objectives in modern nanometer integrated circuit design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. This paper presents: 1) a novel design methodology of applying multi-bit flip-flops at the post-placement stage, which can be seamlessly integrated in modern design flow; 2) a new problem formulation for post-placement optimization with multi-bit flip-flops; 3) flip-flop clustering and placement algorithms to simultaneously minimize flip-flop power consumption and interconnecting wirelength; and 4) a progressive window-based optimization technique to reduce placement deviation and improve runtime efficiency of our algorithms. Experimental results show that our algorithms are very effective in reducing not only flip-flop power consumption but also clock tree and signal net wirelength. Consequently, the power consumption of the clock network is minimized.

原文English
文章編號6071086
頁(從 - 到)1870-1882
頁數13
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
30
發行號12
DOIs
出版狀態Published - 1 十二月 2011

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